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data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 2gb ddr2 C sdram dimm 240 pin dimm seu02g64b3b f 2sa - 2 5 r 2gb pc2 - 6400 in fbga techn ology rohs compliant environmental requirements: ? operating temp erature (ambient) standard grade 0c to 70c ? operating humidity 10% to 90% relative humidity, noncondensing ? operating pressure 105 to 69 kpa (up to 10000 ft.) ? storage temperature - 55c to 100c ? storage humidity 5% to 95% relative humidity, non condensing ? storage pressure 1682 psi (up to 5000 ft.) at 50c options: ? data rate / latency marking ddr2 800 mt/s c l6 - 25 ddr2 6 67 mt/s cl5 - 30 ? module density 2048mb with 16 dies and 2 ranks ? standard grade (t a ) 0c to 70c (t c ) 0c to 85c features: ? 240 - pin 64 - bit dual - in - line double data rate synchronous dram module ? module organization: dual rank 256m x 64 ? v dd = 1 .8v 0. 1 v, v ddq 1.8v 0.1 v ? 1.8v i/o ( sstl_18 compatible) ? auto refresh (cbr) and self refresh 8k refresh every 64ms ? serial presence detect with eeprom ? gold - contact pad ? this module is fully pin and functional compatible to the jedec pc2 - 64 00 spec. and jede c - standard mo - 237. (see www.jedec.org ) ? the pcb and all components are manufactured according to the rohs compliance specification [eu directive 2002/95/ec restriction of hazardous substances (rohs)] ? ddr2 - sdram compone nt samsung k4t1g084qf die rev. f ? 128mx8 ddr2 sdram in fbga - 60 package ? 4 - bit prefetch architecture ? dll to align dq and dqs transitions with ck ? multiple internal device banks for concurrent operation ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency C 1 t ck ? programmable burst length: 4 or 8 ? adjustable data - output drive strength ? on - die termination (odt) figure: mechanical dimensions 1 1 if no tolerances specified 0.15mm
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 this swissbit module is an industry standard 240 - pin 8 - byte ddr2 sdram dual - in - line memory module ( u dimm) which i s organized as x64 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr2 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr2 sdram modules operate from a differential clock (ck a nd ck#). read and write accesses to a ddr2 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. the burst length is either four or eight locations. an auto prechar ge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr2 sdram devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. a self r efresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_18 compatible. the ddr2 sdram module uses the optional serial presence detect (spd) function implemented via serial eeprom using the stand ard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the dimm manufacturer (swissbit) to identify the module type, the modules organization and several timing parameters. the second 128 bytes are availa ble to the end user. module configuration organization ddr2 sdrams used row addr. device bank addr. column addr. refresh module bank select 256m x 64bit 16 x 128m x 8bit ( 1024m bit) 14 ba0, ba1, ba2 10 8k s0#, s1# module dimensions in mm 133.35 (long ) x 30(high) x 4.00 [max] (thickness) timing parameters part number module density transfer rate clock cycle /data bit rate latency seu02g64b3b f 2sa - 25r 2048 mb 6.4 gb/s 2.5ns/800mt/s 6 - 6 - 6 seu02g64b3b f 2sa - 30r 2048 mb 5.3 gb/s 3.0ns/667mt/s 5 - 5 - 5 pin name a0 - 9, a11 C a13 address inputs a10/ap address input / autoprecharge bit ba0 C ba2 bank address inputs dq0 C dq63 data input / output dm0 - dm7 input data mask dqs0 - dqs7 data strobe, positive line dqs0# - dqs7# data strobe, negative line (only us ed when differential data strobe mode is enabled) ras# row address strobe cas# column address strobe we# write enable cke0 C cke1 clock enable s0#, s1# chip select ck0 C ck 2 clock inputs, positive line ck0# - ck 2 # clock inputs, negative line figure 1: mechanical dimensions
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 v dd su pply voltage (1.8v 0.1v) v ref input / output reference v ss ground v ddspd serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa1 presence detect address inputs odt0, odt1 on - die ter mination nc no connection pin configuration pin # front side pin # back side pin # front side pin # back side 1 v ref 121 v ss 61 a4 181 v dd q 2 v ss 122 dq4 62 v dd q 182 a3 3 dq0 123 dq5 63 a2 183 a1 4 dq1 124 v ss 64 v dd 184 v dd 5 v ss 125 dm0 (dqs9 ) 65 v ss 185 ck0 6 dqs0# 126 nc (dqs9#) 66 v ss 186 ck0# 7 dqs0 127 v ss 67 v dd 187 v dd 8 v ss 128 dq6 68 nc (par_in) 188 a0 9 dq2 129 dq7 69 v dd 189 v dd 10 dq3 130 v ss 70 a10/ap 190 ba1 11 v ss 131 dq12 71 ba0 191 v dd q 12 dq8 132 dq13 72 v dd q 192 ras# 13 dq9 133 v ss 73 we# 193 s0# 14 v ss 134 dm1 (dqs10) 74 cas# 194 v dd q 15 dqs1# 135 nc (dqs10#) 75 v dd q 195 odt0 16 dqs1 136 v ss 76 s1# 196 a13 17 v ss 137 ck 1 77 odt1 197 v dd 18 nc(reset#) 138 ck1# 78 v dd q 198 v ss 19 nc 139 v ss 79 v ss 199 dq36 20 v s s 140 dq14 80 dq32 200 dq37 21 dq10 141 dq15 81 dq33 201 v ss 22 dq11 142 v ss 82 v ss 202 dm4 (dqs13) 23 v ss 143 dq20 83 dqs4# 203 nc (dqs13#) 24 dq16 144 dq21 84 dqs4 204 v ss 25 dq17 145 v ss 85 v ss 205 dq38 26 v ss 146 dm2 (dqs11) 86 dq34 206 dq39 27 dqs2# 147 nc (dqs11#) 87 dq35 207 v ss 28 dqs2 148 v ss 88 v ss 208 dq44 29 v ss 149 dq22 89 dq40 209 dq45 30 dq18 150 dq23 90 dq41 210 v ss 31 dq19 151 v ss 91 v ss 211 dm5 (dqs14) 32 v ss 152 dq28 92 dqs5# 212 nc (dqs14#)
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 pin # front side pin # back side p in # front side pin # back side 33 dq24 153 dq29 93 dqs5 213 v ss 34 dq25 154 v ss 94 v ss 214 dq46 35 v ss 155 dm3 (dqs12) 95 dq42 215 dq47 36 dqs3# 156 nc (dqs12#) 96 dq43 216 v ss 37 dqs3 157 v ss 97 v ss 217 dq52 38 v ss 158 dq30 98 dq48 218 dq53 39 dq2 6 159 dq31 99 dq49 219 v ss 40 dq27 160 v ss 100 v ss 220 ck2 41 v ss 161 nc (cb4) 101 sa2 221 ck2# 42 nc (cb0) 162 nc (cb5) 102 nc (test) 222 v ss 43 nc (cb1) 163 v ss 103 v ss 223 dm6 (dqs15) 44 v ss 164 nc (dm8,dqs17) 104 dqs6# 224 nc (dqs15#) 4 5 nc (dqs8#) 165 nc (dqs17#) 105 dqs6 225 v ss 46 nc (dqs8) 166 v ss 106 v ss 226 dq54 47 v ss 167 nc (cb6) 107 dq50 227 dq55 48 nc (cb2) 168 nc (cb7) 108 dq51 228 v ss 49 nc (cb3) 169 v ss 109 v ss 229 dq60 50 v ss 170 v dd q 110 dq56 230 dq61 51 v dd 171 cke1 111 dq57 231 v ss 52 cke0 172 v dd 112 v ss 232 dm7 (dqs16) 53 v dd 173 nc (a15) 113 dqs7# 233 nc (dqs16#) 54 ba2 174 nc (a14) 114 dqs7 234 v ss 55 nc(par_out) 175 v dd q 115 v ss 235 dq62 56 v dd q 176 a12 116 dq58 236 dq63 57 a11 177 a9 117 dq59 237 v ss 58 a7 178 v dd 118 v ss 238 v dd spd 59 v dd 179 a8 119 sda 239 sa0 60 a5 180 a6 120 scl 240 sa1 (sig): signal in brackets may be routed to the socket connector, but is not used on the module
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 functional block diagramm 2048mb ddr2 sdram dimm, 2 ranks and 1 6 components
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 maximum electrical dc characteristics parameter/ condition symbol min max units supply voltage v dd - 1.0 2.3 v i/o supply voltage v dd q - 0.5 2.3 v v dd l supply voltage v dd l - 0.5 2.3 v voltage on any pin relative to v ss v in , v out - 0.5 2.3 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 40 40 ck, ck# - 20 20 dm - 5 5 output leakage current (dqs and odt ar e disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 16 16 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v dd q 1.7 1.8 1.9 v v dd l supply voltage v dd l 1.7 1.8 1.9 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt v ref C ref v ref + 0.04 v input high (logic 1) voltage v ih (dc) v ref + 0.125 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.25 - v input low (logic 0) voltage v il (ac) - v ref - 0.25 v cap acitance at ddr2 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realis tic than a gross estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 i dd specifications and conditions (0c t case + 85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) parameter & test condition symbol max. unit 6400 - 666 5300 - 555 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 440 424 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 488 464 ma precharge power - down current: all device b anks idle; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref i dd2p 160 160 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 320 320 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once ever y two clock cycles; dq inputs changing once per clock cycle i dd2n 400 384 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast pdn exit mr[1 2] = 0 i dd3p 368 352 ma slow pdn exit mr[12] = 1 240 240 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inpu ts are changing once every two clock cycles; dq inputs changing once per clock cycle i dd3n 512 480 ma operating read current *) : all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 720 640 ma
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 parameter & test condition symbol max. uni t 6400 - 666 5300 - 555 operating write current *) : all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid co mmands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 616 560 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid comm ands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 1680 1600 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd6 160 160 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1360 1240 ma *) value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 6400 - 666 5300 - 555 unit cl (i dd ) 6 5 t ck t rcd (i dd ) 15 15 ns t rc (i dd ) 60 60 ns t rrd (i dd ) 7.5 7.5 ns t ck (i dd ) 2.5 3.0 ns t ras min (i dd ) 45 45 ns t ras max (i dd ) 70 000 70 000 ns t rp (i dd ) 15 15 ns t rfc (i dd ) 127.5 127.5 ns
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and recommended ac operating conditions (0c t case + 85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 6400 - 666 5300 - 555 parameter symbol min max min max unit clock cycle time cl = 6 t ck (6) 2.5 8.0 - - ns cl = 5 t ck (5) 3.0 - 8.0 - 3.0 8.0 ns cl = 4 t ck (4) 3.7 5 8.0 3.75 8.0 ns cl = 3 t ck (3) - - 5.0 8.0 ns ck high - level width t ch 0.48 0.52 0.48 0.52 t ck ck low - level width t cl 0.48 0.52 0.48 0.52 t ck half clock period t hp min (t ch, t cl ) min (t ch, t cl ) ps access window (output) of dq s from ck/ck# t ac - 0.40 +0.40 - 0.45 +0.45 ns data - out high - impedance window from ck/ck# t hz t ac max +0.45 (= t ac max) ns data - out low - impedance window from ck/ck# t lz t ac min t ac max - 0.45 (= t ac min) +0.45 (= t ac max) ns dq and dm input setup time relative to dqs t ds 0 .05 0.10 ns dq and dm input hold time relative to dqs t dh 0.125 0.175 ns dq and dm input pulse width ( for each input ) t dipw 0.35 0.35 t ck data hold skew factor t qhs 0.3 0.34 ns dq - dqs hold, dqs to first dq to go non - valid, per access t qh t hp - t qhs t hp - t qhs ns data valid output window t dvw t qh - t dqsq t qh - t dqsq ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs f alling edge from ck rising - hold time t dsh 0.2 0.2 t ck dqs C t dqsq 0.2 0.24 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck dqs write preamble t wpre 0. 35 0.35 t ck dqs write preamble setup time t wpres 0 0 ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck positive dqs latching edge to associated clock edge t dqss - 0.25 + 0.25 - 0.25 + 0.25 t ck write command to first dqs latching transition wl - t dqs s wl+ t dqss wl - t dqss wl+ t dqss t ck address and control input pulse width ( for each input ) t ipw 0.6 0.6 t ck address and control input setup time t is 0.175 0.2 ns
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and recommended ac operating condi tions (continued) (0c t case + 85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 6400 - 666 5300 - 555 parameter symbol min max min max unit address and control input hold time t ih 0.25 0.275 ns cas# to cas# command delay t ccd 2 2 t ck active to active (same bank) command period t rc 60 60 ns active bank a to active bank b command t rrd 7.5 7.5 ns active to read or write delay t rcd 15 15 ns four bank activate period t faw 37.5 37.5 ns active to precharge command t ras 45 70 t rtp 7.5 7.5 ns write recovery time t wr 15 15 ns auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp ns internal write to read command delay t wtr 7.5 7.5 ns precharge command p eriod t rp 15 15 ns precharge all command period t rpa t rp + t ck t rp + t ck ns load mode command cycle time t mrd 2 2 t ck cke low to ck, ck# uncertainty t delay t is + t ck + t ih t is + t ck + t ih t ck refresh to active or refresh to refresh command interv al t rfc 127.5 70 0 c t case 85 c t refi 7.8 7.8 s 85 c < t case 95 c 3.9 3.9 exit self refresh to non - read command t xsnr t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 200 t ck exit self refresh timing referenc e t isxr t is t is ps odt turn - on delay t aond 2 2 2 2 t ck odt turn - on t aon t ac (min) t ac (max) + 1,000 t ac (min) t ac (max) + 1,000 ps odt turn - off delay t aofd 2.5 2.5 2.5 2.5 t ck odt turn - off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps odt turn - on (power - down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt turn - off (power - down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power - down entry latency t anpd 3 3 t ck
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 6400 - 666 5300 - 55 5 parameter symbol min max min max unit odt power - down exit latency t axpd 8 8 t ck odt enable from mrs command t mod 12 12 ns exit active power - down to read command, mr [bit 12 = 0] t xard 2 2 t ck exit active power - down to read command, mr [bit 1 2 = 1] t xards 8 C ck exit precharge power - down to any non - read command t xp 2 2 t ck cke minimum high/low time t cke 3 3 t ck
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 serial presence - detect matrix byte description 6400 - 666 5300 - 555 0 number of spd bytes used 0x80 1 total n umber of bytes in spd device 0x08 2 fundamental memory type 0x08 3 number of row addresses on assembly 0x0e 4 number of column addresses on assembly 0x0a 5 dimm hight and module ranks 0x61 6 module data width 0x40 7 module data width (continued) 0x0 0 8 module voltage interface levels (v dd q ) 0x05 9 sdram cycle time, (t ck ) [max cl] cas latency = 6 ( 64 00), cl = 5 ( 53 00) 0x25 0x30 10 sdram access from clock, (t ac ) [max cl] cas latency = 6 ( 64 00); cl = 5 ( 53 00) 0x40 0x45 11 module configuration type 0x00 12 refresh rate / type 0x82 13 sdram device width (primary sdram) 0x08 14 error - checking sdram data width 0x00 15 minimum clock delay, back - to - back random column access 0x00 16 burst lengths supported 0x0c 17 number of banks on sdram device 0x 08 18 cas latencies supported 0x70 0x38 19 module thickness 0x01 20 ddr2 dimm type 0x02 21 sdram module attributes 0x00 22 sdram device attributes: weak driver and 50 odt 0x07 23 sdram cycle time, (t ck ) [max cl C 1] cas latency = 5 ( 64 00), cl = 4 ( 5 3 00) 0x30 0x3d 24 sdram access from ck, (t ac ) [max cl C 1] cas latency = 5 (6400), cl = 4 (5300) 0x45 0x50 25 sdram cycle time, (t ck ) [max cl C 2] cas latency = 4 (6400), cl = 3 (5300) 0x3d 0x50 26 sdram access from ck, (t ac ) [max cl C 2] cas latency = 4 (6400), cl = 3 (5300) 0x50 0x60 27 minimum row precharge time, (t rp ) 0x3c 28 minimum row active to row active, (t rrd ) 0x1e 29 minimum ras# to cas# delay, (t rcd ) 0x3c 30 minimum ras# pulse width, (t ras ) 0x2d 31 module bank density 0x01
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 serial presence - dtect matrix (continued) byte description 6400 - 666 5300 - 555 32 address and command setup time, (t isb ) 0x17 0x20 33 address and command hold time, (t ihb ) 0x25 0x27 34 data / data mask input setup time, (t dsb ) 0x05 0x10 35 data / data mask inp ut hold time, (t dhb ) 0x12 0x17 36 write recovery time, (t wr ) 0x3c 37 write to read command delay, (t wtr ) 0x1e 38 read to precharge command delay, (t rtp ) 0x1e 39 mem analysis probe 0x00 40 extension for bytes 41 and 42 0x06 41 min active auto refresh time, (t rc ) 0x3c 42 minimum auto refresh to active / auto refresh command period, (t rfc) 0x7f 43 sdram device max cycle time, (t ckmax ) 0x80 44 sdram device max dqs - dq skew time, (t dqsq ) 0x14 0x18 45 sdram device max read data hold skew factor, (t qhs ) 0x1e 0x22 46 pll relock time 0x00 47 - 61 optional features, not supported 0x00 62 spd revision 0x12 63 checksum for bytes 0 - 62 0xe1 0x17 64 - 6 6 manufacturer`s jedec id code 0x 7f 6 7 manufacturer`s jedec id code (continued) 0xda 72 manufacturing locatio n 0x 00 73 - 90 module part number (ascii) seu02g64b3bf 2sa - xx 91 pcb identification code x 92 identification code (continued) x 93 year of manufacture in bcd x 94 week of manufacture in bcd x 95 - 98 module serial number x 99 - 127 manufacturer - specific data (rsvd) x 128 - 255 open for customer use 0xff part number code s e u 02g 64 b3 b f 2 sa - 2 5 * r 1 2 3 4 5 6 7 8 9 10 11 12 13 locations *rohs compl. swissbit ag ddr2 - 800m t/s sdram d dr 2 240 pin unbuffered 1.8v chip vendor (samsung) depth (2048mb) 2 module ranks width chip rev. f pcb - type ( b62urce ) chip organisation x8 * optional / additional information
data sheet rev.1. 1 18.11 .2010 swissbit ag industiestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 14 swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 __________ ___________________ swissbit na, inc. 14 willett avenue, suite 301a port chester, ny 10573 usa phone: +1 914 935 1400 fax: +1 914 935 9865 _____________________________ swissbit na, inc. 3913 todd lane, suite C 307 austin, tx 78744 usa phone: +1 512 30 2 9001 fax: +1 512 302 4808 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512

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